Keynote Speakers
Viktor K. Prasanna
Charles Lee Powell Chair in Engineering
Director, Center for Energy Informatics (CEI)
Professor of Electrical Engineering, Computer Engineering Division, and Professor of Computer Science
University of Southern California
Brief Speaker Bio :
Viktor K. Prasanna (ceng.usc.edu/~prasanna) is Charles Lee Powell Chair in Engineering in the Ming Hsieh Department of Electrical and Computer Engineering and Professor of Computer Science at the University of Southern California. He is the director of the Center for Energy Informatics at USC and leads the FPGA (fpga.usc.edu) and Data Science Labs (dslab.usc.edu). His research interests include parallel and distributed computing, accelerator design, reconfigurable architectures and algorithms and high performance computing. He served as the Editor-in-Chief of the IEEE Transactions on Computers during 2003-06 and is currently the Editor-in-Chief of the Journal of Parallel and Distributed Computing. Prasanna was the founding Chair of the IEEE Computer Society Technical Committee on Parallel Processing. He is the Steering Chair of the IEEE International Parallel and Distributed Processing Symposium (www.ipdps.org) and the Steering Chair of the IEEE International Conference on High Performance Computing (www.hipc.org). His work has received best paper awards at leading forums in parallel computing, HPC and FPGAs, including ACM/IEEE Computing Frontiers, International Parallel and Distributed Processing Symposium, ACM International Symposium on FPGAs, among others. He is a Fellow of the IEEE, the ACM and the American Association for Advancement of Science (AAAS). He is a recipient of 2009 Outstanding Engineering Alumnus Award from the Pennsylvania State University. He received the 2015 W. Wallace McDowell award from the IEEE Computer Society for his contributions to reconfigurable computing.

Title of Talk

Accelerating Data Science at the Edge

Data Science has matured over the past few years with novel applications in diverse areas including health, energy, autonomous x, etc. Many of these are cyber physical social systems with strict requirements of latency, throughput and energy efficiency. In many applications, the computations need to be performed at the “edge” as the data is collected. With recent dramatic advances in Field Programmable Gate Arrays (FPGAs), these devices are being used along with multi-core and novel memory technologies to realize advanced platforms to accelerate complex applications. This talk will review our recent work in the Data Science Lab at USC (dslab.usc.edu) and advances in reconfigurable computing (fpga.usc.edu) leading up to current trends in accelerators for data science. We will illustrate FPGA-based parallel architectures and algorithms for a variety of data analytics kernels in streaming graph processing and machine learning for “edge” processing. While demonstrating algorithm-architecture co-design methodology to realize high performance accelerators for graphs and machine learning, we demonstrate the role of modeling and algorithmic optimizations to develop highly efficient Intellectual Property (IP) cores. We show improved performance for two broad classes of graph analytics: iterative graph algorithms with variable workload (e. g., graph traversal, shortest paths, etc.) and machine learning on graphs (e. g., graph embedding). For variable workload iterative graph algorithms, we illustrate dynamic algorithm adaptation to exploit heterogeneity in the architecture. For graph embedding, we develop a novel computationally efficient technique using graph sampling and demonstrate scalable performance. We conclude by identifying opportunities and challenges in exploiting emerging heterogeneous architectures composed of multi-core processors, FPGAs, GPUs and coherent memory.

Ram D. Sriram
Chief, Software and Systems Division
Information Technology Laboratory
National Institute of Standards and Technology (NIST)
Brief Speaker Bio :
Ram D. Sriram is currently the chief of the Software and Systems Division, Information Technology Laboratory, at the National Institute of Standards and Technology (NIST). Before joining the Software and Systems Division, Sriram was a group leader in the Manufacturing Engineering Laboratory, where he conducted research on standards for interoperability of CAD/CAE/CAM systems. Prior to joining NIST, he was on the engineering faculty (1986-1994) at the Massachusetts Institute of Technology (MIT) and was instrumental in setting up the Intelligent Engineering Systems Laboratory. Sriram has co-authored or authored more than 250 publications, including several books on artificial intelligence. Sriram was a founding co-editor of the International Journal for AI in Engineering. Sriram received several awards including: an NSF’s Presidential Young Investigator Award (1989); ASME Design Automation Award (2011); ASME CIE Distinguished Service Award (2014); the Washington Academy of Sciences’ Distinguished Career in Engineering Sciences Award (2015); ASME CIE division’s Lifetime Achievement Award (2016); and CMU CEE Lt. Col. Christopher Raible Distinguished Public Service Award (2018). Sriram is a Fellow of ASME, AAAS, IEEE and Washington Academy of Sciences, a Distinguished Member (life) of ACM and a Senior Member (life) of AAAI. Sriram has a B.Tech. from IIT, Madras, India, and an M.S. and a Ph.D. from Carnegie Mellon University, Pittsburgh, USA.

Title of Talk

Big Data, Ontologies, and Machine Learning

The advent of social networking and advances in sensors, storage architectures and high speed Internet are resulting in massive amounts of data – big data -- being generated. The “big data” issue can be viewed along seven dimensions: 1. volume, 2. velocity, 3. variety, 4. veracity, 5. value, 6. viewpoint, and 7. visualization. Interpretation, manipulation, and interoperability of data are some of the major concerns facing the data deluge problem. Common reusable content (ontologies) and ontological analysis techniques can address many challenges posed by “big data.” Many machine learning techniques, such as deep neural networks, can aid in developing ontologies. Further, ontologies can be used to develop faster and better machine learning techniques. A major concern with current machine learning techniques is trust. Trust can be developed through a rigorous verification and validation methodology. An executive order, signed by President Trump on Feb. 11, 2019, directs NIST to create “a plan for Federal engagement in the development of technical standards and related tools in support of reliable, robust, and trustworthy systems that use AI technologies.” In this talk, I will focus on various ongoing activities at NIST in the area of big data, ontologies, and machine learning. Particular topics include: Improving measurements techniques, which generate terabytes of image data, used in cell biology; Using a Root&Rule-based technique based on Panini’s grammar for generating ontologies; Applying category theory for knowledge representation; Extending co-occurrence and rule-based methods through machine learning for extracting protein-protein interactions from literature; Comparing the efficiency of transfer learning, generative adversarial networks, and augmentation for achieving desirable AI model accuracy; and Generating rules from neural networks.
Invited Speakers
Srinivas Aluru
Professor and Interim Chair, School of Computational Science and Engineering
Co-Executive Director, Institute for Data Engineering and Science
Georgia Institute of Technology
Brief Speaker Bio :
Srinivas Aluru is co-Executive Director of the Georgia Tech Interdisciplinary Research Institute (IRI) in Data Engineering and Science (IDEaS) and a professor in the School of Computational Science and Engineering within the College of Computing. He co-leads the NSF South Big Data Regional Innovation Hub which nurtures big data partnerships between organizations in the 16 Southern States and Washington D.C., and the NSF Transdisciplinary Research Institute for Advancing Data Science. Aluru conducts research in high performance computing, data science, bioinformatics and systems biology, combinatorial scientific computing, and applied algorithms. He pioneered the development of parallel methods in computational biology, and contributed to the assembly and analysis of complex plant genomes. His group is currently focused on developing bioinformatics methods for high-throughput DNA sequencing, particularly error correction and genome assembly. In systems biology, his group is working on network inference methods using mutual information and Bayesian approaches, and network analysis techniques to further the knowledge of partially characterized pathways. His contributions in scientific computing lie in parallel Fast Multipole Method, domain decomposition methods, spatial data structures, and applications in computational electromagnetics and materials informatics. Aluru is a Fellow of the American Association for the Advancement of Science (AAAS) and the Institute for Electrical and Electronic Engineers (IEEE). He is a recipient of the NSF Career award (1997), IBM faculty award (2002), Swarnajayanti fellowship from the Government of India (2007), and the John. V. Atanasoff Discovery Award from Iowa State University (2017). He serves on the editorial boards of the IEEE Transactions on Big Data, ACM/IEEE Transactions on Computational Biology and Bioinformatics, the Journal of Parallel and Distributed Computing, and the International Journal of Data Mining and Bioinformatics.

Previously, Aluru held faculty positions at Iowa State University, Indian Institute of Technology Bombay, New Mexico State University, and Syracuse University. Immediately prior to joining Georgia Tech, Aluru spent 14 years working as a faculty in the Department of Electrical and Computer Engineering at Iowa State University. At Iowa State, he held the Ross Martin Mehl and Marylyne Munas Mehl endowed professorship (2009-2013) and the Richard Stanley Chair in Interdisciplinary Engineering in the College of Engineering (2006-2009). He chaired the interdepartmental Bioinformatics and Computational Biology graduate program (2005-2007), served as associate chair for research in the department (2003-2006), and led the Dean's Research Initiative in high-throughput computational biology, a multi-disciplinary and multi-investigator initiative at the interface of high performance computing and computational biology. He was a recipient of university level awards for Outstanding Achievement in Research (2011) and Mid-career Achievement in Research (2006), Young Engineering Faculty Research Award (2002) within the College of Engineering, and the Warren B. Boast Undergraduate Teaching Award (2005).

Dr. Jaideep Ganguly, Sc.D.(MIT)
Director of Technology
Amazon, Hyderabad Telangana
Brief Speaker Bio :
Dr. Jaideep Ganguly is a Director of Technology at Amazon, Hyderabad. He is an Innovative, hands-on, have the ability to dive deep. Results-oriented visionary with a distinguished track record in software engineering and machine learning. Strong track record of leading design and implementation of massively scalable and reliable software services. Ability to hire and retain world class talent across distributed dev centers.

Rama Govindaraju
Director of Engineering
Google AI
Brief Speaker Bio :
Rama is a Director of Engineering at Google where he leads the Platforms Performance Engineering team. Prior to that Rama was a Distinguished Engineer at IBM responsible for leading the Software Architecture at IBM's Supercomputing Lab where he led the development of 5 generations of Supercomputers. Prior to that Rama received his MS and Phd in Computer Science from Rensselaer Polytechnic Institute in New York and BE in Computer Science from BIT Mesra, Ranchi, India.

Ananth Kalyanaraman
Professor, and Boeing Centennial Chair in Computer Science
Associate Director
School of Electrical Engineering and Computer Science
Pullman, WA 99164
Brief Speaker Bio :
Ananth Kalyanaraman is a Professor and Boeing Centennial Chair in Computer Science at the School of Electrical Engineering and Computer Science, Washington State University in Pullman. He also holds affiliate faculty positions at the Molecular Plant Sciences Graduate Program and the Paul G. Allen School for Global Animal Health. He also currently serves as the Associate Director for the School of EECS. Ananth received his bachelors from Visvesvaraya National Institute of Technology in Nagpur, India (B.E. in Computer Science and Engineering, 1998); and subsequently M.S. (Computer Science, 2002) and Ph.D. (Computer Engineering, 2006) from Iowa State University.

Ananth works at the intersection of parallel computing, graph analytics, and bioinformatics/computational biology. His focus is on developing algorithms and software for scalable analysis of large-scale data from various scientific domains and particularly the life sciences. Research in his lab has been supported by various funding sources including the National Science Foundation (NSF), U.S. Department of Energy (DOE), U.S. Department of Agriculture (USDA), and the Center for Disease Control and Prevention (CDC). Ananth is a recipient of U.S. Department of Energy Early Career Research Award, and his student-led research works have received multiple conference best paper awards and a prestigious graph challenge award. Ananth serves on the editorial boards of several reputed journals (including TPDS, JPDC, ParCo), and also regularly serves in various capacities including organizational capacities at various conferences in the areas of parallel processing and bioinformatics. He is currently serving as a Vice-Chair for the IEEE Technical Committee on Parallel Programming (TCPP). Ananth is a member of ACM, IEEE and SIAM.

Dhabaleswar K. (DK) Panda
Professor and University Distinguished Scholar of Computer Science and Engineering
The Ohio State University
Brief Speaker Bio :
DK Panda is a Professor and University Distinguished Scholar of Computer Science and Engineering at the Ohio State University. He has published over 450 papers in the area of high-end computing and networking. The MVAPICH2 (High Performance MPI and PGAS over InfiniBand, Omni-Path, iWARP and RoCE) libraries, designed and developed by his research group (http://mvapich.cse.ohio-state.edu), are currently being used by more than 3,000 organizations worldwide (in 89 countries). More than 600,000 downloads of this software have taken place from the project's site. This software is empowering several InfiniBand clusters (including the 3rd, 5th, 8th, 16th, and 19th ranked ones) in the TOP500 list. The RDMA packages for Apache Spark, Apache Hadoop and Memcached together with OSU HiBD benchmarks from his group (http://hibd.cse.ohio-state.edu) are also publicly available. These libraries are currently being used by more than 315 organizations in 35 countries. More than 31,600 downloads of these libraries have taken place. High-performance and scalable versions of the Caffe and TensorFlow framework are available from https://hidl.cse.ohio-state.edu. Prof. Panda is an IEEE Fellow. More details about Prof. Panda are available at http://www.cse.ohio-state.edu/~panda.

Title of Talk

Scalable and Distributed DNN Training on Modern HPC Systems

This talk will start with an overview of challenges being faced by the AI community to achieve scalable and distributed DNN training on Modern HPC systems. After that, the talk will focus on a range of solutions being carried out in my group to address these challenges. The solutions will include: 1) MPI-driven Deep Learning, 2) Co-designing Deep Learning Stacks with High-Performance MPI, 3) Out-of-core DNN training, 4) Accelerating TensorFlow on HPC Systems, 5) Accelerating Big Data Stacks, and 6) Efficient Deep Learning over Big Data.

Laxmidhar Behera
Department of Electrical Engineering
Indian Institute of Technology - Kanpur
Brief Speaker Bio :
Dr. Laxmidhar Behera is currently associated with the Department of Electrical Engineering as a Professor in the Control and Automation Specialization. He heads the Intelligent Systems and Control Laboratory at IIT Kanpur and extensively focuses on developing automation solutions to industrial and deomstic problems.

Sanjay Ranka
University of Florida
Brief Speaker Bio :
Sanjay Ranka is a Professor in the Department of Computer Information Science and Engineering at University of Florida. His current research interests are high performance and parallel computing with a focus on energy efficiency; and big data science with a focus on data mining/machine learning algorithms for spatiotemporal applications. His work is driven by applications in CFD, remote sensing, health care and transportation. He teaches courses on data science (three course curriculum), data mining and parallel computing.

From 1999-2002, he was the Chief Technology Officer at Paramark (Sunnyvale, CA). At Paramark, he developed a real-time optimization service called PILOT for marketing campaigns. PILOT served more than 10 million optimized decisions a day in 2002 with a 99.99% uptime. Paramark was recognized by VentureWire/Technologic Partners as a top 100 Internet technology company in 2001 and 2002 and was acquired in 2002. He has also held positions as a tenured faculty positions at Syracuse University and as a researcher/visitor at IBM T.J. Watson Research Labs and Hitachi America Limited.

Sanjay earned his Ph.D. (Computer Science) from the University of Minnesota and a B. Tech. in Computer Science from IIT, Kanpur, India. He has coauthored four books, 250+ journal and refereed conference articles. His recent co-authored work has received a best student paper runner up award at IGARSS 2015, best paper award at BICOB 2014, best student paper award at ACM-BCB 2010, best paper runner up award at KDD-2009, a nomination for the Robbins Prize for the best paper in journal of Physics in Medicine and Biology for 2008, and a best paper award at ICN 2007.

He is a fellow of the IEEE and AAAS, and a past member of IFIP Committee on System Modeling and Optimization. He is an associate Editor-in-Chief of the Journal of Parallel and Distributed Computing and an associate editor for ACM Computing Surveys, IEEE/ACM Transactions on Computational Biology and Bioinformatics, Sustainable Computing: Systems and Informatics, Knowledge and Information Systems, and International Journal of Computing. He is also an edittorial board member of Applied Sciences (Compuing and Artificial Intelligence). Additionally, he is a book series editor for CRC Press for Bigdata. In the past, he has been an associate editor for IEEE Transactions on Parallel and Distributed Systems and IEEE Transactions on Computers.

He was a past member of the IFIP Committee on System Modeling and Optimization, Parallel Compiler Runtime Consortium, the Message Passing Initiative Standards Committee and Technical Committee on Parallel Processing. He is the program chair for 2015 High Performance Computing, 2013 International Parallel and Distributed Processing Symposium, 2010 International Conference on Contemporary Computing and co-general chair for 2009 International Conference on Data Mining and 2010 International Conference on Green Computing. He is a series editor for CRC press on Bigdata. His work has received 11500+ citations with an h-index of 52 (based on Google Scholar).

Title of Talk

Machine Learning for Smart Transportation

In this talk, I will present our research on our work on a multi-sensor system for vehicle and pedestrian traffic analysis and visualization at intersections to discover trajectory patterns and anomalous traffic behavior. Augmenting these data with signal and phasing information, we show how clustering in the context of signal information may help us to detect anomalies with respect to vehicles violating signals. The system is being leveraged by several other applications, including conflict detection in object movements, turn movement counts, incident detection and management, and demand profiling, for better traffic management through the adjustment of signal timing.

Ananda Deshmukh
Lead AI
Tech Mahindra
Brief Speaker Bio :
Ananda Deshmukh is currently associated with the Tech Mahindra as a Lead AI.

Arya K Bhattacharya
Dean of Research and Professor
Mahindra École Centrale
Brief Speaker Bio :
Dr. Arya Kumar Bhattacharya is the Dean of Research and Professor in the School of Engineering Sciences. He has been with the Institute since inception in 2014. He has with him more than twenty years of industrial experience, including at Defence Research and Development Organization (ADA - Bangalore), Alstom Transport (UK) and at Tata Steel (Automation Division, Jamshedpur), all in Research and Development roles at different levels. He has been AICTE-INAE Distinguished Visiting Professor at Birla Institute of Technology, Mesra.

Prof. Arya has filed for more than twenty patents and published more than thirty-five papers in Journals, International Conferences and book chapters. His chapter in the book Evolutionary Computation published by InTech has been downloaded more than 9000 times since 2010, according to the Publisher. His multi-disciplinary research interests cover Machine Learning, Evolutionary Algorithms, Game Theory, and Autonomous Systems applied to different domains like Aerospace, Manufacturing and Industry 4.0, Logistics, Transportation and others.